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NXP Semiconductors /MIMXRT1052 /TRNG /INT_MASK

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Interpret as INT_MASK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HW_ERR_0)HW_ERR 0 (ENT_VAL_0)ENT_VAL 0 (FRQ_CT_FAIL_0)FRQ_CT_FAIL

FRQ_CT_FAIL=FRQ_CT_FAIL_0, HW_ERR=HW_ERR_0, ENT_VAL=ENT_VAL_0

Description

Mask Register

Fields

HW_ERR

Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted.

0 (HW_ERR_0): Corresponding interrupt of INT_STATUS is masked.

1 (HW_ERR_1): Corresponding bit of INT_STATUS is active.
ENT_VAL

Same behavior as bit 0 of this register.

0 (ENT_VAL_0): Same behavior as bit 0 of this register.

1 (ENT_VAL_1): Same behavior as bit 0 of this register.
FRQ_CT_FAIL

Same behavior as bit 0 of this register.

0 (FRQ_CT_FAIL_0): Same behavior as bit 0 of this register.

1 (FRQ_CT_FAIL_1): Same behavior as bit 0 of this register.

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data